1. Field of the Invention
The present invention relates to a drive circuit and a drive method for use in a plane display apparatus, particularly of the type that indicates gray-scale in accordance with digital video data.
2. Description of the Prior Art
When a liquid crystal display apparatus (hereinafter referred to as "LCD apparatus") is driven, the speed of response of the liquid crystal is slower than a luminescent material used in a CRT (cathode ray tube) display apparatus. To compensate for the slow response speed, special drive circuits are often used. One such liquid crystal drive circuit does not supply video data in succession to pixels but holds the data as signal voltages for a period of time after the data has been sampled up to the horizontal period of time (the horizontal period of time is the time that is required for a video signal to be sampled for all pixels on a horizontal scanning line). The video signal voltages are then output to all of the pixels on one scanning line at the same time, which may be at the initial moment of the horizontal period of time or at an appropriate point of time within the horizontal period of time. The video signal voltages delivered to the corresponding pixels are held for a period of time exceeding the response speed of the liquid crystal, thereby allowing the liquid crystal fully to assume the desired orientation.
One known drive circuit uses capacitors to hold video signal voltage. FIG. 47 shows a signal voltage output circuit (a source driver) for supplying drive voltages V.sub.S to N pixels on a selected scanning line. The signal voltage output circuit for each pixel is composed of a first analog switch SW.sub.1, a sampling capacitor C.sub.SMP, a second analog switch SW.sub.2, a holding capacitor C.sub.H, and an output-buffer amplifier A. This known signal output circuit will be described below with reference to the circuit diagram of FIGS. 47 and 48 and to the timing chart of FIG. 49.
An analog video data V.sub.S input to the first analog switch SW.sub.1 is sequentially sampled by the switch in accordance with a corresponding sampling clock signal T.sub.SMP1 to T.sub.SMPN which correspond to the N pixels on one scanning line selected by a horizontal synchronizing signal H.sub.syn. By this sampling, the sequential instantaneous voltages V.sub.SMP1 to voltages V.sub.SMPN of the video data signal V.sub.s are applied to the corresponding sampling capacitors C.sub.SMP. For example, the nth sampling capacitor C.sub.SMP will be charged to the voltage V.sub.SMPn of the video signal V.sub.S when the analog switch SW.sub.1 corresponding to the nth pixel, receives a signal T.sub.SMPN an.sub.d will hold-this value. The signal voltages V.sub.SMP1 to V.sub.SMPN which are sequentially sampled and held in one horizontal period of time are transferred from the sampling capacitors C.sub.SMP to the holding capacitors C.sub.H, when an output pulse OE is supplied to all of the analog switches SW.sub.2 at the same time. Then the signal voltages V.sub.SMP1 to V.sub.SMPN are output to source lines O.sub.1 to O.sub.N connected to the respective pixels through the buffer amplifiers A.
The drive circuit described above, which is supplied with analog video data, suffers from the following problems when the size and resolution of the liquid crystal panel are increased:
(1) When the charges in the sampling capacitors C.sub.SMP are transferred to the holding capacitors C.sub.H, the relationship between the voltage V.sub.H of the holding capacitor C.sub.H and the sampled voltage V.sub.SMP is represented ed by the following equation: ##EQU1##
Accordingly, in order to ensure that voltage V.sub.H held by the holding capacitor C.sub.H becomes equal to the sampled voltage V.sub.SMP, a condition of C.sub.SMP &gt;&gt;C.sub.H must be satisfied, i.e., the capacitance of the capacitor C.sub.SMP must be much greater than the capacitance of capacitor C.sub.H. To this end, it is necessary to use a sampling capacitor C.sub.SMP of a relatively large capacitance. However, if the capacitance of the sampling capacitor C.sub.SMP is too large, the period of time required for charging (i.e. a sampling period of time) is prolonged. However, as the size of the LCD apparatus becomes larger or the resolution is improved, the number of pixels corresponding to one horizontal period of time increases, thereby necessitating the shortening of the sampling time. Consequently, there is a limit to the increase in size or the improvement in resolution of the LCD apparatus.
(2) Analog video data are supplied to the source driver via bus lines. As the size and resolution of a display apparatus are increased, the frequency band of the video signal becomes wider and the distribution capacity of the bus lines increases. This requires a wideband amplifier in the circuit for supplying video data, thereby increasing the cost of production.
(3) A color display apparatus using RGB video data has bus lines for supplying multiple analog color video data. As the size and resolution of the display panel of such an apparatus are increased, the wideband amplifiers must have an extremely high signal quality so that no phase difference occurs from data to data and no dispersion occurs in the amplitude and frequency characteristics.
(4) In the drive circuit for a matrix type display apparatus, unlike the display in a CRT, analog video data is sampled in accordance with a clock signal and displayed in pixels arranged in a matrix. At this time, since the bus lines unavoidably cause delays of clock signals in the drive circuit, it is difficult to locate the sampling position exactly for the analog video data. Particularly, when a computer graphic image is displayed in which the video data and pixel addresses must exactly correspond to each other, any displacement in the image display position, blurring of the image, or any other faults caused by the signal delay in the drive system and deterioration of the frequency characteristics are fatal problems.
These problems which occur when using analog video data can be solved by digitizing the video signals. To supply digital data, the drive circuit shown in FIGS. 50 and 51 can be used. For simplicity, two bits (D.sub.1, D.sub.0) of data are illustrated. The video data thus has one of four values 0 to 3, and a signal voltage applied to each pixel is one of the four levels V.sub.0 to V.sub.3. FIG. 50 shows a digital source driver circuit equivalent to the analog source driver circuit shown in FIG. 47. The circuit diagram of FIG. 50 shows the entire source driver for supplying a driving voltage to N pixels. FIG. 51 shows a portion of the circuit for the nth pixel. This portion of the circuit comprises a D-type flip-flop (sampling flip-flop) M.sub.SMP at a first stage and a flip-flop (holding flip-flop) M.sub.H at a second stage which are provided with the respective bits (D.sub.1, D.sub.0) of the video data, a decoder DEC, and analog switches ASW.sub.0 to ASW.sub.3 corresponding to four external voltage sources V.sub.0 to V.sub.3 and a source lane 0.sub.n. For the sampling of digital video data, various circuit components other than a D-type flip-flop can be used.
The digital source driver operates as follows:
The sampling flip-flop M.sub.SMP samples the video data (D.sub.1, D.sub.0) at the rising edge of a sampling pulse T.sub.SMPn corresponding to the nth pixel. When the sampling for one horizontal period of time is completed, an output pulse OE is fed to the holding flip-flop M.sub.H. All the video data (D.sub.1, D.sub.0) held in the holding flip-flops M.sub.H are then simultaneously output to the respective decoders DEC. Each of the decoders DEC decodes the 2-bit video data (D.sub.1, D.sub.0). In accordance with the values 0 to 3, one of the analog switches ASW.sub.0 to ASW.sub.3 closes, and the corresponding one of the four external voltages V.sub.0 to V.sub.3 is output to the source line O.sub.n.
The source driver using video data for sampling has solved problems 1 to 4 occurring in the use of analog video data for sampling, but nevertheless the following other problems arise:
(1) With an increase in the number of bits of video data, the size of the memory cells, decoders, etc. constituting a drive circuit becomes large.
(2) When voltage sources V.sub.0 to V.sub.3 supplied from outside in FIGS. 50 and 51 are selected by analog switches, the selected voltage source is directly connected to a source line of the liquid crystal panel and drives it. Accordingly, the circuit must drive a large load like the liquid crystal panel. However, it is difficult to obtain such a high power within the LSI which must be supplied with power from outside. This increases the production cost. As the number of bits increases, the number of the voltage sources increases by 2.sup.n. As a result, an increase in the number of bits raises production cost. For example, when four-bit data (D.sub.0 to D.sub.3) is used and a 16 gray-scale is indicated, the source driver is constructed as shown in FIG. 52 which requires a signal voltage (V.sub.0 to V.sub.15) with 2.sup.4 (i.e. 16) levels. This requires sixteen voltage sources.
(3) In proportion to the increase in the number of voltage sources by 2.sup.2, the number of input terminals constituting the driver circuit increases. For example, if the data is extended from 5-bits to 6-bits, the number of voltage sources (the number of input terminals) will increase from 2.sup.5 (32) up to 2.sup.6 (64). This makes it difficult to fabricate LSIs. In addition, the mounting and production of such LSIs become difficult. As a result, mass production becomes difficult. As the video data is composed of a greater number of bits, the number of analog switches increases by 2.sup.2. In addition, an ON resister is required to be inserted between the voltage source and the source line. It is desirable to minimize the resistance of the ON resister but there is a limit to the reduction of the size. As a result, the size of The chip cannot be reduced beyond a certain extent. As the number of components is increased, the power compsumption of the circuit correspondingly increases.